RTL Design/Verilog 연습
4 bit Comparator / 32 bit Comparator
유로 청년
2024. 6. 30. 14:09
1. 4 bit Comparator (Dataflow Modeling)
< Source >
// Dataflow Modeling of 4bit Comparator
module Comparator_4bit_Dataflow_Modeling(
input [3:0] a, b,
output equal, greater, less );
assign equal = (a == b)? 1 : 0;
assign greater = (a > b)? 1 : 0;
assign less = (a < b)? 1 : 0;
endmodule
< RTL Analysis >
2. 32 bit Comparator (Dataflow Modeling)
< Source >
// Dataflow Modeling of 32 bit Comparator.
module Comparator_32bit_Dataflow_Modeling(
input [31:0] a, b,
output equal, greater, less);
assign equal = (a == b)? 1 : 0;
assign greater = (a > b)? 1 : 0;
assign less = (a < b)? 1 : 0;
endmodule
< RTL Analysis >