RTL Design/Verilog 연습
T Flip Flop
유로 청년
2024. 7. 11. 20:08
1. Behavioral Modeling of T Flip Flop (Positive edge sensitive)
< Source code >
// Behavioral modeling of T Flip Flop
module Behavioral_Modeling_of_T_Flip_Flop_Positive(
input t,
input clk, enable, reset,
output reg q );
always @(posedge clk or posedge reset) begin
if(reset) q = 0;
else if(enable) q = (t)? ~q : q;
else q = q;
end
endmodule
< Simulation >
< RTL analysis >
< Synthesis >
2. Behavioral Modeling of T Flip Flop (Negative edge sensitive)
< Source code >
// Behavioral Modeling of T Flip Flop
module Behavioral_Modeling_of_T_Flip_Flop_Negative(
input t,
input clk, reset, enable,
output reg q );
always @(negedge clk or posedge reset) begin
if(reset) q = 0;
else if(enable) q = (t)? ~q : q;
else q = q;
end
endmodule
< Simulation >
< RTL analysis >
< Synthesis >