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목록왜 d flip flop을 기반으로 counter를 설계하는가? (1)
거북이처럼 천천히
Verilog RTL 설계(7월 12일 - 3, 동기식 카운터 - 2)
1. Synchronous MOD-16 Up Counter implemented with T - Flip Flop// Behavioral modeling of T Flip Flopmodule t_flip_flop ( input t, input clk, enable, reset_p, output reg q); always @(posedge clk or posedge reset_p) begin if(reset_p) q = 0; else if(enable) q = (t)? ~q : q; else q = q; end endmodule// Synchronous MOD-16 Up Counter implemented with T Flip-..
RTL Design/Verilog RTL 설계
2024. 7. 14. 14:01