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목록dataflow modeling에서는 if문을 사용할 수 없다. (1)
거북이처럼 천천히
4 bit parallel adder / subtractor
1. Structural Modeling of 4 bit parallel adder / subtractor// Behavioral Modeling of and gate.module and_gate ( input a, b, output reg out); always @(a, b) begin case({a, b}) 2'b00 : out = 0; 2'b01 : out = 0; 2'b10 : out = 0; 2'b11 : out = 1; endcase endendmodule// Behavioral Modeling of xor gatemodule xor_gate ( input..
RTL Design/Verilog 연습
2024. 6. 30. 11:51