Notice
Recent Posts
Recent Comments
Link
| 일 | 월 | 화 | 수 | 목 | 금 | 토 |
|---|---|---|---|---|---|---|
| 1 | 2 | 3 | 4 | 5 | ||
| 6 | 7 | 8 | 9 | 10 | 11 | 12 |
| 13 | 14 | 15 | 16 | 17 | 18 | 19 |
| 20 | 21 | 22 | 23 | 24 | 25 | 26 |
| 27 | 28 | 29 | 30 |
Tags
- DHT11
- BASYS3
- i2c 통신
- hc-sr04
- verilog
- Recursion
- structural modeling
- KEYPAD
- half adder
- Edge Detector
- FND
- ring counter
- prescaling
- Pspice
- Algorithm
- behavioral modeling
- soc 설계
- gpio
- test bench
- D Flip Flop
- LED
- Linked List
- vivado
- atmega 128a
- java
- ATMEGA128A
- stop watch
- pwm
- uart 통신
- dataflow modeling
Archives
- Today
- Total
목록synchronous mod-16 down counter (1)
거북이처럼 천천히
Verilog RTL 설계(7월 12일 - 3, 동기식 카운터 - 2)
1. Synchronous MOD-16 Up Counter implemented with T - Flip Flop// Behavioral modeling of T Flip Flopmodule t_flip_flop ( input t, input clk, enable, reset_p, output reg q); always @(posedge clk or posedge reset_p) begin if(reset_p) q = 0; else if(enable) q = (t)? ~q : q; else q = q; end endmodule// Synchronous MOD-16 Up Counter implemented with T Flip-..
RTL Design/Verilog RTL 설계
2024. 7. 14. 14:01