Notice
Recent Posts
Recent Comments
Link
| 일 | 월 | 화 | 수 | 목 | 금 | 토 |
|---|---|---|---|---|---|---|
| 1 | 2 | 3 | 4 | 5 | 6 | 7 |
| 8 | 9 | 10 | 11 | 12 | 13 | 14 |
| 15 | 16 | 17 | 18 | 19 | 20 | 21 |
| 22 | 23 | 24 | 25 | 26 | 27 | 28 |
| 29 | 30 |
Tags
- prescaling
- atmega 128a
- structural modeling
- ring counter
- Algorithm
- hc-sr04
- Edge Detector
- D Flip Flop
- test bench
- gpio
- vivado
- Linked List
- verilog
- ATMEGA128A
- KEYPAD
- pwm
- half adder
- dataflow modeling
- uart 통신
- i2c 통신
- soc 설계
- Pspice
- DHT11
- stop watch
- BASYS3
- LED
- FND
- Recursion
- java
- behavioral modeling
Archives
- Today
- Total
목록up-down counter (1)
거북이처럼 천천히
Verilog RTL 설계(7월 12일 - 5, 동기식 업/다운 카운터)
1. Synchronous Up Down Counter (Negative edge trigger)Up counter로 동작하며, Down Counter로서 동작할 수 있다. // Syncrhronous Up Down Counter implemented with D Flip Flopmodule Synchronous_Up_Down_Counter_Negative( input up_down, input clk, enable, reset_p, output reg [3:0] count ); // 0 : Up Counting, 1 : Down Counting always @(negedge clk or posedge reset_p) begin if(reset_p) coun..
RTL Design/Verilog RTL 설계
2024. 7. 14. 20:19