Notice
Recent Posts
Recent Comments
Link
| 일 | 월 | 화 | 수 | 목 | 금 | 토 |
|---|---|---|---|---|---|---|
| 1 | 2 | 3 | 4 | 5 | 6 | 7 |
| 8 | 9 | 10 | 11 | 12 | 13 | 14 |
| 15 | 16 | 17 | 18 | 19 | 20 | 21 |
| 22 | 23 | 24 | 25 | 26 | 27 | 28 |
| 29 | 30 |
Tags
- gpio
- test bench
- Edge Detector
- verilog
- Pspice
- stop watch
- uart 통신
- ring counter
- soc 설계
- Algorithm
- DHT11
- BASYS3
- pwm
- LED
- atmega 128a
- Linked List
- half adder
- D Flip Flop
- Recursion
- prescaling
- FND
- hc-sr04
- KEYPAD
- java
- ATMEGA128A
- structural modeling
- i2c 통신
- vivado
- dataflow modeling
- behavioral modeling
Archives
- Today
- Total
목록4bit comparator (1)
거북이처럼 천천히
4 bit Comparator / 32 bit Comparator
1. 4 bit Comparator (Dataflow Modeling)// Dataflow Modeling of 4bit Comparatormodule Comparator_4bit_Dataflow_Modeling( input [3:0] a, b, output equal, greater, less ); assign equal = (a == b)? 1 : 0; assign greater = (a > b)? 1 : 0; assign less = (a 2. 32 bit Comparator (Dataflow Modeling)// Dataflow Modeling of 32 bit Comparator.module Comparator_32bit_Dataflow_Modelin..
RTL Design/Verilog 연습
2024. 6. 30. 14:09