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목록verilog의 비교 연산자 (1)
거북이처럼 천천히
![](http://i1.daumcdn.net/thumb/C150x150/?fname=https://blog.kakaocdn.net/dn/lhP3w/btsH1nxVFWa/19eLxZxyc7A5dCiEaZLag1/img.png)
1. 1bit Comparator1bit 비교기는 1bit 데이터 2개를 입력받아 두 값을 비교하여 1) A > B인지 2) A == B인지 3) A 1bit 비교기의 Truth table 과 논리 회로는 다음과 같다. 2. 1bit Comparator ( Behavior modeling )module comparator_1bit_behavior_modeling( input a, b, output reg equal, greater, less ); always @(*) begin case({a, b}) 2'b00 : begin equal = 1; greater = 0; less = 0; end ..
Verilog/Verilog RTL 설계
2024. 6. 15. 16:02