Notice
Recent Posts
Tags
- Method
- structure
- fast pwm mode
- Recursion
- sequential logic circuit
- Linked List
- ATMEGA128A
- half adder
- atmega 128
- ctc mode
- verilog
- Algorithm
- MUX
- 4bit parallel adder
- behavioral modeling
- Comparator
- full adder
- LED
- interrupt
- structural modeling
- Set
- java
- interface
- dataflow modeling
- normal mode
- behavior modeling
- timer / counter
- 8bit timer/counter
- atmega 128a
- gpio
거북이처럼 천천히
Module with parameters 본문
1. Module with parametes (N bit comparator)
< Source >
// Module with parameter
module Module_with_parameters #(parameter N=8)(
input [N-1:0] a, b,
output equal, greater, less);
assign equal = (a == b)? 1 : 0;
assign greater = (a > b)? 1 :0;
assign less = (a < b)? 1 : 0;
endmodule
2. 4 bit Comparator by using module with parameter
< Source >
// Module with parameter
module Module_with_parameters #(parameter N=8)(
input [N-1:0] a, b,
output equal, greater, less);
assign equal = (a == b)? 1 : 0;
assign greater = (a > b)? 1 :0;
assign less = (a < b)? 1 : 0;
endmodule
// 4bit Comparator
module comparator_4bit_by_using_parameter_module (
input [3:0] a, b,
output equal, greater, less);
Module_with_parameters #(.N(4)) comparator(.a(a), .b(b), .equal(equal), .greater(greater), .less(less));
endmodule
< Simulation >
< RTL analysis >
< Synthesis >
'Verilog > Verilog 연습' 카테고리의 다른 글
4 X 2 Encoder / 2 X 4 Decoder (0) | 2024.07.01 |
---|---|
4 bit Comparator / 32 bit Comparator (0) | 2024.06.30 |
1 bit Comparator (0) | 2024.06.30 |
4 bit parallel adder / subtractor (0) | 2024.06.30 |
4 bit parallel adder (0) | 2024.06.30 |