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Module with parameters 본문

Verilog/Verilog 연습

Module with parameters

유로 청년 2024. 6. 30. 17:42

1. Module with parametes (N bit comparator)

< Source >

// Module with parameter
module Module_with_parameters #(parameter N=8)(
    input [N-1:0] a, b,
    output equal, greater, less);
    
    assign equal = (a == b)? 1 : 0;
    assign greater = (a > b)? 1 :0;
    assign less = (a < b)? 1 : 0;
    
endmodule

 

 

2. 4 bit Comparator by using module with parameter

< Source >

// Module with parameter
module Module_with_parameters #(parameter N=8)(
    input [N-1:0] a, b,
    output equal, greater, less);
    
    assign equal = (a == b)? 1 : 0;
    assign greater = (a > b)? 1 :0;
    assign less = (a < b)? 1 : 0;
    
endmodule

// 4bit Comparator 
module comparator_4bit_by_using_parameter_module (
    input [3:0] a, b,
    output equal, greater, less);
    
    Module_with_parameters #(.N(4)) comparator(.a(a), .b(b), .equal(equal), .greater(greater), .less(less));
    
endmodule

 

 

< Simulation >

 

 

< RTL analysis >

 

 

< Synthesis >

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