1 bit Comparator

1. 1 bit Comparator (by using case)

<Source>

// Behavioral Modeling of 1bit comparator (by using case)
module Comparator_1bit_Behavioral_Modeling_by_using_case(
    input a, b,
    output reg equal, greater, less);
    
    always @(a, b) begin
        case({a, b}) 
            2'b00 : begin equal = 1; greater = 0; less = 0; end
            2'b01 : begin equal = 0; greater = 0; less = 1; end
            2'b10 : begin equal = 0; greater = 1; less = 0; end
            2'b11 : begin equal = 1; greater = 0; less = 0; end
        endcase
    end
    
endmodule

 

<Simulation>

 

<RTL Analysis>

 

<Synthesis>

 

 

 

 

 

 

 

2. 1 bit Comparator (by using if-else)

<Source>

module Comparator_1bit_Behavioral_Modeling_by_using_if_else(
    input a, b,
    output reg equal, greater, less);
    
    always @(a, b) begin
           if(a == b) begin equal = 1; greater = 0; less = 0; end
           else if(a > b) begin equal = 0; greater = 1; less = 0; end
           else begin equal = 0; greater = 0; less = 1; end
    end
    
endmodule

 

<Simulation>

 

<RTL Analysis>

 

 

<Synthesis>

 

 

 

 

 

 

 

 

 

3. 1 bit Comparator (Structural Modeling)

<Source>

// Behavioral Modeling of xnor gate.
module xnor_gate (
    input a, b,
    output reg out);
    
    always @(a, b) begin
        case({a, b})
            2'b00 : out = 1;
            2'b01 : out = 0;
            2'b10 : out = 0;
            2'b11 : out = 1;
        endcase
    end    
endmodule

// Behavioral Modeling of and gate.
module and_gate (
    input a, b,
    output reg out);
    
    always @(a, b) begin
        case({a, b})
            2'b00 : out = 0;
            2'b01 : out = 0;
            2'b10 : out = 0;
            2'b11 : out = 1;
        endcase
    end      
endmodule


// Structural Modeling of 1 bit Comparator.
module Comparator_1bit_Structural_Modeling(
    input a, b,
    output equal, greater, less );
    
    xnor_gate xnor0 (a, b, equal);
    and_gate and0 (a, ~b, greater);
    and_gate and1 (~a, b, less); 
    
endmodule

 

<Simulation>

 

<RTL Analysis>

 

 

<Synthesis>

 

 

 

 

 

4. 1 bit Comparator (Dataflow Modeling)

<Source>

// Dataflow Modeling of 1 bit Comparator.
module Comparator_1bit_Dataflow_Modeling(
    input a, b,
    output equal, greater, less );
    
    assign equal = (a==b)? 1 : 0;
    assign greater = (a>b)? 1 : 0;
    assign less = (a<b)? 1 : 0;
    
endmodule

 

<Simulation>

 

<RTL Analysis>

 

 

<Synthesis>