4 bit parallel adder

1. Structural Modeling of 4 bit parallel adder

<Source>

// Behavioral Modeling of and gate
module and_gate  (
    input a, b,
    output reg out);
    
    always @(a, b) begin
        case({a, b}) 
            2'b00 :  out = 0;
            2'b01 :  out = 0;
            2'b10 :  out = 0;
            2'b11 :  out = 1;
        endcase
    end     
endmodule

// Behavioral Modeling of xor gate.
module xor_gate (
    input a, b,
    output reg out);
    
    always @(a, b) begin 
        case({a, b}) 
            2'b00 : out = 0;
            2'b01 : out = 1;
            2'b10 : out = 1;
            2'b11 : out = 0;
        endcase
    end
endmodule

// Behavioral Modeling of or gate.
module or_gate (
    input a, b,
    output reg out);
    
    always @(a, b) begin
        case({a, b}) 
            2'b00 : out = 0;
            2'b01 : out = 1;
            2'b10 : out = 1;
            2'b11 : out = 1;
        endcase
    end 
 endmodule
 
 // Structural Modeling of Half adder.
 module half_adder (
    input a, b,
    output sum, carry);
    
    and_gate and0 (a, b, carry);
    xor_gate xor0 (a, b, sum);
    
 endmodule
 
 // Structural Modeling of Full adder
 module full_adder (
    input a, b, Cin,
    output sum, carry);
    
    wire sum_0, carry_0, carry_1;
    
    half_adder half0 (a, b, sum_0, carry_0);
    half_adder half1 (Cin, sum_0, sum, carry_1);
    
    or_gate or0 (carry_0, carry_1, carry);
    
endmodule

// Structural Modeling of 4 bit parallel adder
module Parallel_4bit_adder_Structural_Modeling(
    input [3:0] a, b,
    input Cin,
    output [3:0] sum,
    output carry );
    
    wire [2:0] carry_of_full_adder;
    
    full_adder full_adder0 (a[0], b[0], Cin, sum[0], carry_of_full_adder[0]);
    full_adder full_adder1 (a[1], b[1], carry_of_full_adder[0], sum[1], carry_of_full_adder[1]);
    full_adder full_adder2 (a[2], b[2], carry_of_full_adder[1], sum[2], carry_of_full_adder[2]);
    full_adder full_adder3 (a[3], b[3], carry_of_full_adder[2], sum[3], carry_of_full_adder[3]);
    
endmodule

 

 

<Simulation>

 

<RTL Analysis>

 

<Synthesis>

 

 

 

 

 

 

 

 

2. Dataflow Modeling of 4 bit parallel adder

 

<Source>

// Dataflow Modeling of 4bit parallel adder
module Parallel_4bit_adder_Dataflow_Modeling(
    input [3:0] a, b,
    input Cin,
    output [3:0] sum,
    output carry);
    
    wire [4:0] result = a + b + Cin;
    
    assign sum = result[3:0];
    assign carry = result[4];
    
endmodule

 

<Simulation>

 

<RTL Analysis>

 

<Synthesis>

 

 

 

 

 

3. Behavioral Modeling of 4 bit parallel adder

• 입력 데이터 : 4 bit 크기를 갖는 a, b와 1 bit 크기를 갖는 Cin
• 따라서 모든 경우의 수를 따져보기 위해서는 총 2^9 = 512가지의 입력 값을 줘야 한다.
• 그런데, 512가지의 입력에 대해서 출력을 정의하는 것은 힘들기 때문에 해당 설계 방식은 넘어간다.