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거북이처럼 천천히
4 X 1 MUX와 4 X 1 DEMUX의 조합 본문
1. Behavioral modeling of combination of 4X1 MUX and 1X4 DEMUX (case)
< Source code >
// Behavioral Modeling of MUX
module mux (
input[3:0] signal,
input[1:0] selector,
output reg data );
always @(*) begin
case(selector)
2'b00 : data = signal[0];
2'b01 : data = signal[1];
2'b10 : data = signal[2];
2'b11 : data = signal[3];
default data = data;
endcase
end
endmodule
// Behavioral Modeling of DEMUX
module demux (
input data,
input[1:0] selector,
output reg [3:0] signal );
always @(*) begin
case(selector)
2'b00 : signal = {3'b000, data};
2'b01 : signal = {2'b00, data, 1'b0};
2'b10 : signal = {1'b0, data, 2'b00};
2'b11 : signal = {data, 3'b000};
default signal = signal;
endcase
end
endmodule
// Behavioral Modeling of Combination of MUX & DEMUX
module Combination_of_MUX_AND_DEMUX_Behavioral_Modeling_case(
input[3:0] input_signal,
input[1:0] mux_selector, demux_selector,
output[3:0] output_signal );
wire wire_between_mux_and_demux;
mux mux0 (input_signal, mux_selector, wire_between_mux_and_demux);
demux demux0 (wire_between_mux_and_demux, demux_selector, output_signal);
endmodule
< Simulation >
MUX selector : 0, DEMUX selector : 2
MUX selector : 1, DEMUX selector : 2
< RTL analysis >
< Synthesis >
2. Behavioral modeling of combination of 4X1 MUX and 1X4 DEMUX (if-else)
< Source code >
// Behavioral Modeling of MUX
module mux (
input [3:0] signal,
input [1:0] selector,
output reg data );
always @(*) begin
if(selector == 2'b00) data = signal[0];
else if(selector == 2'b01) data = signal[1];
else if(selector == 2'b10) data = signal[2];
else if(selector == 2'b11) data = signal[3];
else data = data;
end
endmodule
// Behavioral Modeling of DEMUX
module demux (
input data,
input [1:0] selector,
output reg [3:0] signal );
always @(*) begin
if(selector == 2'b00) signal = {3'b000, data};
else if(selector == 2'b01) signal = {2'b00, data, 1'b0};
else if(selector == 2'b10) signal = {1'b0, data, 2'b00};
else if(selector == 2'b11) signal = {data, 3'b000};
else signal = signal;
end
endmodule
// Behavioral Modeling of Combination of MUX & DEMUX
module Combination_of_MUX_AND_DEMUX_Behavioral_Modeling_if_else(
input [3:0] input_signal,
input [1:0] mux_selector, demux_selector,
output [3:0] output_signal );
wire wire_of_linking_between_MUX_and_DEMUX;
mux mux0 (input_signal, mux_selector, wire_of_linking_between_MUX_and_DEMUX);
demux demux0 (wire_of_linking_between_MUX_and_DEMUX, demux_selector, output_signal);
endmodule
< Simulation >
MUX selector : 1, DEMUX selector : 3
MUX selector : 2, DEMUX selector : 2
< RTL analysis >
< Synthesis >
3. Dataflow modeling of combination of 4X1 MUX and 1X4 DEMUX (조건 연산자)
< Source code >
// Dataflow modeling of combination of 4X1 MUX and 1x4 DEMUX
module Dataflow_modeling_of_combination_of_4X1_MUX_and_1X4_DEMUX_3_condition(
input [3:0] input_signal,
input [1:0] mux_selector, demux_selector,
output [3:0] output_signal );
wire wire_of_MUX_and_DEMUX;
assign wire_of_MUX_and_DEMUX = (mux_selector == 2'b00)? input_signal[0] :
((mux_selector == 2'b01)? input_signal[1] :
((mux_selector == 2'b10)? input_signal[2] :
((mux_selector == 2'b11)? input_signal[3] : input_signal[0])));
assign output_signal = (demux_selector == 2'b00)? {3'b000, wire_of_MUX_and_DEMUX} :
((demux_selector == 2'b01)? {2'b00, wire_of_MUX_and_DEMUX, 1'b0} :
((demux_selector == 2'b10)? {1'b0, wire_of_MUX_and_DEMUX, 2'b00} :
((demux_selector == 2'b11)? {wire_of_MUX_and_DEMUX, 3'b000} : output_signal)));
endmodule
< Simulation >
MUX selector : 1, DEMUX selector : 0
MUX selector : 2, DEMUX selector : 3
< RTL analysis >
4. Dataflow modeling of combination of 4X1 MUX and 1X4 DEMUX (배열 인덱스)
< Source code >
// Dataflow modeling of combination of 4X1 MUX and 1X4 DEMUX
module Dataflow_modeling_of_combination_of_4X1_MUX_and_1X4_DEMUX_array_index(
input [3:0] input_signal,
input [1:0] mux_selector, demux_selector,
output [3:0] output_signal );
wire wire_of_mux_and_demux;
assign wire_of_mux_and_demux = input_signal[mux_selector];
assign output_signal = (demux_selector == 2'b00)? {3'b000, wire_of_mux_and_demux} :
((demux_selector == 2'b01)? {2'b00, wire_of_mux_and_demux, 1'b0} :
((demux_selector == 2'b10)? {1'b0, wire_of_mux_and_demux, 2'b00} :
((demux_selector == 2'b11)? {wire_of_mux_and_demux, 3'b000} : output_signal)));
endmodule
< Simulation >
MUX selector : 1, DEMUX selector : 2
MUX selector : 1, DEMUX selector : 2
< RTL analysis >
5. Structural modeling of combination of 4X1 MUX and 1X4 DEMUX
< Source code >
// Dataflow modeling of MUX
module mux (
input [3:0] signal,
input [1:0] selector,
output data );
assign data = signal[selector];
endmodule
// Dataflow modeling of DEMUX
module demux (
input data,
input [1:0] selector,
output [3:0] signal );
assign signal = (selector == 2'b00)? {3'b000, data} :
((selector == 2'b01)? {2'b00, data, 1'b0} :
((selector == 2'b10)? {1'b0, data, 2'b00} :
((selector == 2'b11)? {data, 3'b000} : signal )));
endmodule
// Structural modeling of combination of MUX & DEMUX
module Structural_modeling_of_combination_of_4X1_MUX_and_1X4_DEMUX(
input [3:0] input_signal,
input [1:0] mux_selector, demux_selector,
output [3:0] output_signal );
wire link;
mux mux0 (input_signal, mux_selector, link);
demux demux0 (link, demux_selector, output_signal);
endmodule
< Simulation >
MUX selector : 3, DEMUX selector : 2
< RTL analysis >
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