Notice
Recent Posts
Recent Comments
Link
| 일 | 월 | 화 | 수 | 목 | 금 | 토 |
|---|---|---|---|---|---|---|
| 1 | ||||||
| 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| 9 | 10 | 11 | 12 | 13 | 14 | 15 |
| 16 | 17 | 18 | 19 | 20 | 21 | 22 |
| 23 | 24 | 25 | 26 | 27 | 28 | 29 |
| 30 |
Tags
- Recursion
- gpio
- Pspice
- prescaling
- behavioral modeling
- FND
- Edge Detector
- LED
- java
- half adder
- ring counter
- dataflow modeling
- i2c 통신
- KEYPAD
- test bench
- atmega 128a
- vivado
- ATMEGA128A
- hc-sr04
- Linked List
- Algorithm
- BASYS3
- D Flip Flop
- pwm
- soc 설계
- uart 통신
- stop watch
- structural modeling
- DHT11
- verilog
Archives
- Today
- Total
거북이처럼 천천히
JK Flip Flop 본문
1. Behavioral modeling of JK Flip Flop (Positive edge)
< Source code >
// Behavioral modeling of JK Flip Flop
module Behavioral_modeling_of_JK_Flip_Flop_Positive(
input j, k,
input clk, enable, reset,
output reg q );
always @(posedge clk or posedge reset) begin
if(reset) q = 0;
else if(enable) begin
if(j == 0 && k == 0) q = q;
else if(j == 1 && k == 0) q = 1;
else if(j == 0 && k == 1) q = 0;
else q = ~q;
end
else q = q;
end
endmodule
< Simulation >

< RTL analysis >

< Synthesis >

2. Behavioral modeling of JK Flip Flop (Negative edge)
< Source code >
// Behavioral modeling of JK Flip Flop
module Behavioral_Modeling_of_JK_Flip_Flop_Negative(
input j, k,
input clk, enable, reset,
output reg q );
always @(negedge clk or posedge reset) begin
if(reset) q = 0;
else if(enable) begin
if(j == 0 && k ==0) q = q;
else if(j == 0 && k ==1) q = 0;
else if(j == 1 && k ==0) q = 1;
else q = ~q;
end
else q = q;
end
endmodule
< Simulation >

< RTL analysis >

< Synthesis >

'RTL Design > Verilog 연습' 카테고리의 다른 글
| 비동기식 카운터 (Asynchronous counter) (0) | 2024.07.11 |
|---|---|
| T Flip Flop (0) | 2024.07.11 |
| SR Latch / D Latch / D Flip Flop (0) | 2024.07.10 |
| 4 X 1 MUX와 4 X 1 DEMUX의 조합 (0) | 2024.07.09 |
| 4 X 1 MUX / 1 X 4 DEMUX (0) | 2024.07.08 |