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RTL Design/Verilog 연습

T Flip Flop

1. Behavioral Modeling of T Flip Flop (Positive edge sensitive)

< Source code >

// Behavioral modeling of T Flip Flop
module Behavioral_Modeling_of_T_Flip_Flop_Positive(
    input t,
    input clk, enable, reset,
    output reg q  );
    
    always @(posedge clk or posedge reset) begin
        if(reset) q = 0;
        else if(enable) q = (t)? ~q : q;
        else q = q;
    end
    
endmodule

 

< Simulation >

 

< RTL analysis >

 

 

< Synthesis >

 

 

 

 

2. Behavioral Modeling of T Flip Flop (Negative edge sensitive)

 

< Source code >

// Behavioral Modeling of T Flip Flop
module Behavioral_Modeling_of_T_Flip_Flop_Negative(
    input t,
    input clk, reset, enable,
    output reg q  );
    
    always @(negedge clk or posedge reset) begin
        if(reset) q = 0;
        else if(enable) q = (t)? ~q : q;
        else q = q;
    end
    
endmodule

 

< Simulation >

 

< RTL analysis >

 

< Synthesis >

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