Notice
Recent Posts
Recent Comments
Link
| 일 | 월 | 화 | 수 | 목 | 금 | 토 |
|---|---|---|---|---|---|---|
| 1 | ||||||
| 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| 9 | 10 | 11 | 12 | 13 | 14 | 15 |
| 16 | 17 | 18 | 19 | 20 | 21 | 22 |
| 23 | 24 | 25 | 26 | 27 | 28 | 29 |
| 30 |
Tags
- stop watch
- Pspice
- pwm
- FND
- test bench
- uart 통신
- prescaling
- half adder
- atmega 128a
- gpio
- hc-sr04
- java
- i2c 통신
- behavioral modeling
- dataflow modeling
- Recursion
- KEYPAD
- verilog
- structural modeling
- ring counter
- D Flip Flop
- Linked List
- BASYS3
- soc 설계
- ATMEGA128A
- LED
- vivado
- DHT11
- Edge Detector
- Algorithm
Archives
- Today
- Total
거북이처럼 천천히
T Flip Flop 본문
1. Behavioral Modeling of T Flip Flop (Positive edge sensitive)
< Source code >
// Behavioral modeling of T Flip Flop
module Behavioral_Modeling_of_T_Flip_Flop_Positive(
input t,
input clk, enable, reset,
output reg q );
always @(posedge clk or posedge reset) begin
if(reset) q = 0;
else if(enable) q = (t)? ~q : q;
else q = q;
end
endmodule
< Simulation >

< RTL analysis >

< Synthesis >

2. Behavioral Modeling of T Flip Flop (Negative edge sensitive)
< Source code >
// Behavioral Modeling of T Flip Flop
module Behavioral_Modeling_of_T_Flip_Flop_Negative(
input t,
input clk, reset, enable,
output reg q );
always @(negedge clk or posedge reset) begin
if(reset) q = 0;
else if(enable) q = (t)? ~q : q;
else q = q;
end
endmodule
< Simulation >

< RTL analysis >

< Synthesis >

'RTL Design > Verilog 연습' 카테고리의 다른 글
| Normal Clock (0) | 2024.08.04 |
|---|---|
| 비동기식 카운터 (Asynchronous counter) (0) | 2024.07.11 |
| JK Flip Flop (0) | 2024.07.11 |
| SR Latch / D Latch / D Flip Flop (0) | 2024.07.10 |
| 4 X 1 MUX와 4 X 1 DEMUX의 조합 (0) | 2024.07.09 |