- interface
- structural modeling
- java
- full adder
- LED
- structure
- ring counter
- Algorithm
- interrupt
- D Flip Flop
- gpio
- normal mode
- MUX
- fast pwm mode
- atmega 128
- ctc mode
- dataflow modeling
- verilog
- Comparator
- siso shift register
- Method
- atmega 128a
- half adder
- Set
- behavioral modeling
- Linked List
- ATMEGA128A
- Recursion
- Shift Register
- Pspice
목록전체 글 (171)
거북이처럼 천천히
![](http://i1.daumcdn.net/thumb/C150x150/?fname=https://blog.kakaocdn.net/dn/cJ0vyx/btsIjdPdzE0/XkKF1RSX467bjXjAj8DPpK/img.png)
1. 4 bit Comparator (Dataflow Modeling)// Dataflow Modeling of 4bit Comparatormodule Comparator_4bit_Dataflow_Modeling( input [3:0] a, b, output equal, greater, less ); assign equal = (a == b)? 1 : 0; assign greater = (a > b)? 1 : 0; assign less = (a 2. 32 bit Comparator (Dataflow Modeling)// Dataflow Modeling of 32 bit Comparator.module Comparator_32bit_Dataflow_Modelin..
![](http://i1.daumcdn.net/thumb/C150x150/?fname=https://blog.kakaocdn.net/dn/c2t2xs/btsIi9TzJvo/zcrb0BVRzGoGKhK84R3jck/img.png)
1. 1 bit Comparator (by using case)// Behavioral Modeling of 1bit comparator (by using case)module Comparator_1bit_Behavioral_Modeling_by_using_case( input a, b, output reg equal, greater, less); always @(a, b) begin case({a, b}) 2'b00 : begin equal = 1; greater = 0; less = 0; end 2'b01 : begin equal = 0; greater = 0; less = 1; end 2'b10 : be..
![](http://i1.daumcdn.net/thumb/C150x150/?fname=https://blog.kakaocdn.net/dn/xzWLW/btsIhRGlkwU/ZEFLxsTMLdwexevSIUW0Jk/img.png)
1. Structural Modeling of 4 bit parallel adder / subtractor// Behavioral Modeling of and gate.module and_gate ( input a, b, output reg out); always @(a, b) begin case({a, b}) 2'b00 : out = 0; 2'b01 : out = 0; 2'b10 : out = 0; 2'b11 : out = 1; endcase endendmodule// Behavioral Modeling of xor gatemodule xor_gate ( input..
![](http://i1.daumcdn.net/thumb/C150x150/?fname=https://blog.kakaocdn.net/dn/Dj2dO/btsIjcbEW8e/JoGe89E5GiEouA9FFmqsgK/img.png)
1. Structural Modeling of 4 bit parallel adder// Behavioral Modeling of and gatemodule and_gate ( input a, b, output reg out); always @(a, b) begin case({a, b}) 2'b00 : out = 0; 2'b01 : out = 0; 2'b10 : out = 0; 2'b11 : out = 1; endcase end endmodule// Behavioral Modeling of xor gate.module xor_gate ( input a,..
![](http://i1.daumcdn.net/thumb/C150x150/?fname=https://blog.kakaocdn.net/dn/bf8KAC/btsIhWtWB3o/I1s3cloiIQYolQAztOMYb1/img.png)
1. Behavioral Modeling of Full adder// Behavioral modeling of Full addermodule Full_adder_Behavioral_Modeling ( input a, b, Cin, output reg sum, carry); always @(*) begin case({a, b, Cin}) 3'b000 : begin sum = 0; carry = 0; end 3'b001 : begin sum = 1; carry = 0; end 3'b010 : begin sum = 1; carry = 0; end 3'b011 : begin sum = 0; car..