- Linked List
- interface
- ctc mode
- verilog
- normal mode
- Method
- Set
- LED
- Algorithm
- ATMEGA128A
- structure
- atmega 128a
- dataflow modeling
- timer / counter
- half adder
- java
- behavioral modeling
- MUX
- Recursion
- 8bit timer/counter
- structural modeling
- Comparator
- full adder
- gpio
- behavior modeling
- 4bit parallel adder
- fast pwm mode
- sequential logic circuit
- interrupt
- atmega 128
목록Verilog/Verilog 연습 (9)
거북이처럼 천천히
1. Structural Modeling of 4 bit parallel adder// Behavioral Modeling of and gatemodule and_gate ( input a, b, output reg out); always @(a, b) begin case({a, b}) 2'b00 : out = 0; 2'b01 : out = 0; 2'b10 : out = 0; 2'b11 : out = 1; endcase end endmodule// Behavioral Modeling of xor gate.module xor_gate ( input a,..
1. Behavioral Modeling of Full adder// Behavioral modeling of Full addermodule Full_adder_Behavioral_Modeling ( input a, b, Cin, output reg sum, carry); always @(*) begin case({a, b, Cin}) 3'b000 : begin sum = 0; carry = 0; end 3'b001 : begin sum = 1; carry = 0; end 3'b010 : begin sum = 1; carry = 0; end 3'b011 : begin sum = 0; car..
1. Half adder1.1. Behavioral Modeling (by using case)// Behavioral modeling of Half addermodule Half_adder_Behavioral_Modeling( input a, b, output reg carry, sum); always @(a, b) begin case({a, b}) 2'b00 : begin carry = 0; sum = 0;end 2'b01 : begin carry = 0; sum = 1;end 2'b10 : begin carry = 0; sum = 1;end 2'b11 : begin carry = 1; ..
1. AND Gate (Behavior modeling)- Behavior modeling을 통해 AND Gate를 구현- // AND Gate Behavior Modelingmodule AND_Gate_Behavior_Modeling( input a, b, output reg out_value); // input port a, b에 대해서 // 입력 값에 따라 출력 값을 지정함으로서 // 입/출력 값으로 회로를 설계했기 때문에 // 이는 Behavior Modeling이다. always @(a ,b) begin case({a, b}) 2'b00 : o..